Connection to a network using a data processing terminal has been frequently conducted. In accordance with this, a communication system to connect to the network by radio has been developed in a communication apparatus for connecting to the network by radio in particular, has good compatibility with the data processing terminal having a built-in microprocessor, and is often incorporated as a part of the data processing terminal. Therefore, as a condition required for a radio interface, in addition to the condition required for a general communication apparatus, it is necessary to meet the condition required for the data processing terminal, which specifically is a small size, low power consumption, and small generated heat. On the other hand, there is a demand for higher transmission capacity.
As the data processing terminal system in a first conventional example, a “software radio apparatus” is mentioned in Japanese Laid Open Patent Application 2002-64399. The data processing terminal system in the first conventional example has a CPU (Central Processing Unit), an antenna control unit, a RF/IF unit, a D/A converter, and an A/D converter.
In the first conventional example, the CPU is provided for the purpose of controlling a communication function block, and the CPU is not mounted to the data processing terminal system for the purpose of carrying out a general data processing as considered as an original intended purpose of the data processing terminal (for example, the processing other than communication, such as spreadsheet processing and word-processing). For this reason, in the data processing terminal system in the first conventional example, the signal processing section (CPU) is tightly connected through dedicated signal lines, with the antenna control unit, the RF/IF unit, the D/A converter, the A/D converter, and the like, all of which are not configured to be easily taken out.
However, since a function of the communication apparatus is not used when the connection to the network is not carried out, it is desirable that the data processing terminal system has a configuration in which the communication apparatus can be easily attached and detached optionally, in order not to lose portability in using the data processing terminal system as the data processing terminal.
FIG. 1 shows a configuration of the data processing terminal system using a microwave-band quadrature amplitude modulation wave, as the data processing terminal system in a second conventional example. The data processing terminal system in the second conventional example has the antenna 51, a microwave transmitting and receiving unit 17, and a microprocessor signal processing unit 18. The antenna 51 and the microwave transmitting and receiving unit 17 are a transmitting and receiving apparatus (communication apparatus). The microprocessor signal processing unit 18 is a data processing terminal.
The microwave transmitting and receiving unit 17, at the time of reception, demodulates a reception RF (Radio Frequency) signal as a modulation wave received through the antenna 51 to reception data, and outputs the demodulated reception data to the microprocessor signal processing unit 18. The microwave transmitting and receiving unit 17, at the time of transmission, converts transmission data from the microprocessor signal processing unit 18 into a transmission RF signal as the modulation wave, and transmits the converted transmission RF signal through the antenna 51.
The microwave transmitting and receiving unit 17 is provided with a high-frequency processing unit 21, and a modulation and demodulation processing unit 89.
The high-frequency processing unit 21, at the time of the reception, converts the reception RF signal received through the antenna 51 into a reception IF (Intermediate Frequency) signal; and outputs the converted reception IF signal to the modulation and demodulation processing unit 89. The high-frequency processing unit 21, at the time of the transmission, converts a transmission IF signal from the modulation and demodulation processing unit 89 into the transmission RF signal, and outputs the converted transmission RF signal through the antenna 51.
The modulation and demodulation processing unit 89, at the time of the reception, converts the reception IF signal from the high-frequency processing unit 21 into the reception data, and outputs the converted reception data to the microprocessor signal processing unit 18. The modulation and demodulation processing unit 89, at the time of the transmission, converts the transmission data from the microprocessor signal processing unit 18 into the transmission IF signal, and outputs the converted transmission IF signal to the high-frequency processing unit 21.
The high-frequency processing unit 21 is provided with a duplexer (DUP) 52, a low noise amplifier (LNA) 53, band-pass filters (BPF) 54, 56, 60, and 62, frequency converters (CONV) 55 and 61, local oscillators (OSC) 57 and 58, and a power amplifier (PA) 59.
The duplexer (DUP) 52 is provided with a reception signal band-pass filter (not shown) and a transmission signal band-pass filter (not shown).
The local oscillators (OSC) 57 and 58 generate a local oscillation signal.
The modulation and demodulation processing unit 89 is provided with a demodulator (DEM) 70, a modulator (MOD) 23, and a baseband processing unit. The base band processing unit is provided with analog/digital (A/D) converters 24-1 and 24-2, digital/analog (D/A) converters 25-1 and 25-2, a clock generator (CLOCK GEN) 27, a decoder (DEC) 71, an encoder (ENC) 72, and a microwave transmitting and receiving unit interface (I/F) 73.
The demodulator (DEM) 70 is provided with a carrier-wave recovering circuit (not shown) and a reception symbol clock recovering circuit (not shown).
The microwave transmitting and receiving unit interface (I/F) 73 is provided with a reception data buffer circuit (not shown), a transmission data buffer circuit (not shown), an identification data processing circuit (not shown), and a timing adjusting circuit (not shown).
The microprocessor signal processing unit 18 is provided with a clock generator (CLOCK GEN) 30, a microprocessor signal processing unit interface (I/F) 74, and a microprocessor signal processing circuit 75 as a CPU.
The clock generator 30 generates a reference clock, and outputs the generated reference clock to the microprocessor signal processing unit interface 74 and the microprocessor signal processing circuit 75. The microprocessor signal processing unit interface 74 outputs a bus clock signal synchronous with the reference clock, to the microwave transmitting and receiving unit interface 73.
The microprocessor signal processing unit interface 74 is provided with the reception data buffer circuit (not shown), the transmission data buffer circuit (not shown), and the timing adjusting circuit (not shown).
The microprocessor signal processing circuit (CPU) 75 has a microprocessor (not shown), a memory (not shown), an input and output unit (not shown), and the like. A plurality of programs (not shown) are stored in the memory.
The microprocessor signal processing circuit (CPU) 75 carries out the general data processing (processing other than the communication function) based on a general program (for example, a spreadsheet processing program and a word-processing program) (not shown) among a plurality of programs stored in the memory. The data processing terminal system of the second conventional example is configured to be able to attach and detach the microwave transmitting and receiving unit 17. When the general data processing is carried out, the function of the microwave transmitting and receiving unit 17 is not used. For this reason, a user can separate the microwave transmitting and receiving unit 17 and the microprocessor signal processing unit 18, and use the data processing terminal system in the second conventional example as the data processing terminal, only with the function of the microprocessor signal processing unit 18.
Next, an operation when the data processing terminal system in the second conventional example receives a signal will be described.
In the reception signal band-pass filter of the duplexer (DUP) 52, a frequency band of the reception RF signal is set. The reception signal band-pass filter extracts only the reception RF signal received through the antenna 51, and outputs the extracted reception RF signal to the low noise amplifier (LNA) 53. In case of a quadrature amplitude modulation signal (QAM modulation signal), the reception RF signal is a signal having a carrier-wave frequency generated by carrying out quadrature modulation to a reception analog baseband signal (reception analog BB signal) having a symbol frequency (reception symbol frequency), by use of an in-phase carrier wave and a quadrature carrier wave that is shifted by 90 degrees in phase from the in-phase carrier wave.
The low noise amplifier (LNA) 53 amplifies the reception RF signal from the duplexer (DUP) 52 to a level enough for the demodulator (DEM) 70 to carry out a signal processing. The low noise amplifier (LNA) 53 then outputs the amplified reception RF signal to the frequency converter (CONV) 55 through the band-pass filter (BPF) 54. An undesired frequency component other than the carrier-wave frequency band set in the band-pass filter (BPF) 54 is removed from the reception RF signal from the low noise amplifier (LNA) 53.
The frequency converter (CONV) 55 mixes the reception RF signal obtained by removing the undesired frequency component, with the local oscillation signal generated by the local oscillator (OSC) 57 to convert into the reception intermediate frequency signal (reception IF signal). The frequency converter (CONV) 55 outputs the converted reception IF signal to the modulation and demodulation processing unit 89 through the band-pass filter (BPF) 56. The carrier-wave frequency band set in the band-pass filter (BPF) 56 is selected for the reception IF signal from the frequency converter (CONV) 55.
The demodulator (DEM) 70 converts the reception IF signal from the band-pass filter (BPF) 56 into the reception analog baseband signal (reception analog BB signal). In the case of the QAM modulation signal, the demodulator (DEM) 70 recovers the carrier wave of the reception IF signal, and carries out the coherent detection. That is, the carrier-wave recovering circuit of the demodulator (DEM) 70 generates (recovers) the in-phase carrier wave and the quadrature carrier wave from the reception IF signal. The demodulator (DEM) 70 carries out the coherent detection to the QAM modulation waves (the in-phase carrier wave and the quadrature carrier wave) to convert the QAM modulation waves (the in-phase carrier wave and the quadrature carrier wave) into an analog in-phase component signal (analog I signal) and an analog quadrature component signal (analog Q signal) as the reception analog BB signal, and to output the converted analog I signal and analog Q signal to the A/D converters 24-1 and 24-2.
A reception symbol clock recovering circuit of the demodulator (DEM) 70 generates (recovers) the reception symbol clock that has the frequency n times (n is an integer number) larger than the reception symbol frequency, and is superimposed on the reception IF signal. The reception symbol clock recovering circuit of the demodulator (DEM) 70 outputs the generated (recovered) reception symbol clock to the A/D converters 24-1 and 24-2, the decoder (DEC) 71, and the microwave transmitting and receiving unit interface 73.
The A/D converters 24-1 and 24-2 carries out sampling of the analog I signal and the analog Q signal from the demodulator (DEM) 70 by use of a sampling clock synchronous with the reception symbol clock. Thus, the A/D converters 24-1 and 24-2 generates (converts into) a digital in-phase component signal (digital I signal) and a digital quadrature component signal (digital Q signal) as a reception digital baseband signal (reception digital BB signal), and outputs the generated (converted) digital I signal and digital Q signal to the decoder (DEC) 71. The digital in-phase component signal (digital I signal) and the digital quadrature component signal (digital Q signal) correspond to amplitudes of the carrier waves of the analog I signal and the analog Q signal at the time of the sampling.
The decoder (DEC) 71 carries out an error correction process and a decoding process to the digital I signal and the digital Q signal as the reception digital BB signal in synchronization with the reception symbol clock, and outputs the processed digital I signal and digital Q signal to the microwave transmitting and receiving unit interface 73.
The identification data processing circuit of the microwave transmitting and receiving unit interface 73 inputs the reception digital BB signal from the decoder (DEC) 71; generates the reception data to which a removing process of data for signal identification (identification data removing process) in a radio zone has been carried out; and stores the generated reception data in a reception data buffer circuit. The input and output of the microwave transmitting and receiving unit interface 73 is asynchronous. For this reason, the timing adjusting circuit carries out the timing adjusting process for adjusting the timing when the reception data stored in the reception data buffer circuit is outputted to the microprocessor signal processing unit 18. The microwave transmitting and receiving unit interface 73 outputs the reception data to the microprocessor signal processing unit 18 in synchronization with the bus clock from the microprocessor signal processing unit 18.
The microprocessor signal processing unit interface 74 of the microprocessor signal processing unit 18 stores the reception data from the microwave transmitting and receiving unit 17 (microwave transmitting and receiving unit interface 73) in the reception data buffer circuit in synchronization with the reference clock from the clock generator 30. The input and output of the microprocessor signal processing unit interface 74 is asynchronous. For this reason, the timing adjusting circuit carries out the timing adjusting process for adjusting the timing when the reception data stored in the reception data buffer circuit is outputted to the microprocessor signal processing circuit (CPU) 75. The microprocessor signal processing unit interface 74 outputs the reception data to the microprocessor signal processing circuit (CPU) 75 in synchronization with the reference clock from the clock generator 30.
The microprocessor signal processing circuit (CPU) 75 executes an application program (an e-mail processing program, for example) (not shown) among a plurality of programs stored in the memory.
Based on the application program (the e-mail processing program, for example), the microprocessor signal processing circuit (CPU) 75 processes the reception data from the microprocessor signal processing unit interface 74 in synchronization with the reference clock from the clock generator 30.
Next, an operation when the data processing terminal system in the second conventional example transmits a signal will be described.
The microprocessor signal processing circuit (CPU) 75 outputs the transmission data generated based on the application program to the microprocessor signal processing unit interface 74 in synchronization with the reference clock from the clock generator 30.
The microprocessor signal processing unit interface 74 stores the transmission data from the microprocessor signal processing circuit (CPU) 75 in the transmission data buffer circuit in synchronization with the reference clock from the clock generator 30. Since the input and output of the microprocessor signal processing unit interface 74 is asynchronous, the timing adjusting circuit carries out the timing adjusting process for adjusting the timing when the transmission data stored in the transmission data buffer circuit is outputted to the microwave transmitting and receiving unit 17 (the microwave transmitting and receiving unit interface 73). The microprocessor signal processing unit interface 74 outputs the transmission data to the microwave transmitting and receiving unit interface 73 in synchronization with the reference clock from the clock generator 30.
The clock generator 27 generates the transmission symbol clock having a transmission symbol frequency, and outputs the generated transmission symbol clock to the D/A converters 25-1 and 25-2, the encoder (ENC) 72, and the microwave transmitting and receiving unit interface 73.
The microwave transmitting and receiving unit interface 73 stores the transmission data from the microprocessor signal processing unit 18 in the transmission data buffer circuit in synchronization with the bus clock from the microprocessor signal processing unit interface 74. Since the input and output of the microwave transmitting and receiving unit interface 73 is asynchronous, the timing adjusting circuit carries out the timing adjusting process for adjusting the timing when the transmission data stored in the transmission data buffer circuit is outputted to the encoder (ENC) 72. The identification data processing circuit of the microwave transmitting and receiving unit interface 73 carries out a signal identification data adding process (identification data adding process) in the radio zone to the transmission data in synchronization with the transmission symbol clock from the clock generator 27, and outputs the processed transmission data to the encoder (ENC) 72.
The encoder (ENC) 72 carries out a redundant data adding process for the error correction and an encoding process to the transmission data from the microwave transmitting and receiving unit interface 73 in synchronization with the transmission symbol clock from the clock generator 27. The encoder (ENC) 72 then generates the digital I signal and the digital Q signal as the transmission digital baseband signal (transmission digital BB signal), and outputs the generated digital I signal and digital Q signal to the D/A converters 25-1 and 25-2.
The D/A converters 25-1 and 25-2 convert the digital I signal and the digital Q signal into the analog I signal and the analog Q signal as the transmission analog baseband signal (transmission analog BB signal), that show the amplitudes of the carrier waves, in synchronization with the transmission symbol clock from the clock generator 27. Then, the D/A converters 25-1 and 25-2 and outputs the converted analog I signal and analog Q signal to the modulator (MOD 23).
The modulator (MOD) 23 carries out the quadrature modulation to the analog I signal and the analog Q signal as the transmission analog baseband signal (transmission analog BB signal), by use of the in-phase carrier wave and the quadrature carrier wave, and generates the transmission IF signal. The modulator (MOD) 23 then outputs the generated transmission IF signal to the frequency converter (CONV) 61 through the band-pass filter (BPF) 62. At this time, the transmission IF signal is limited to the carrier-wave frequency band that is set in the band-pass filter (BP) 62.
The frequency converter (CONV) 61 mixes the transmission IF signal from the band-pass filter (BPF) 62 with the local oscillation signal generated by the local oscillator (OSC) 58, and converts the mixed transmission IF signal into the transmission RF signal. The frequency converter (CONV) 61 outputs the converted transmission RF signal to the power amplifier (PA) 59 through the band-pass filter (BPF) 60. An undesired frequency component other than the carrier-wave frequency band that is set in the band-pass filter (BPF) 60 is removed from the transmission RF signal from the frequency converter (CONV) 61.
The power amplifier (PA) 59 amplifies transmission power to the extent of a power level necessary to transmit the transmission RF signal, and outputs the transmission RF signal to the duplexer (DUP) 52.
The frequency band of the transmission RF signal is set in a transmission signal band-pass filter of the duplexer (DUP) 52. The transmission signal band-pass filter extracts only the transmission RF signal from the power amplifier (PA) 59, and outputs the extracted transmission RF signal to the network through the antenna 51.
The transmission of the data between the microwave transmitting and receiving unit interface 73 and the microprocessor signal processing unit interface 74 is carried out in synchronization with the reference clock generated by the clock generator 30. The reference clock is asynchronous with the reception symbol clock generated by the demodulator (DEM) 70 and the transmission symbol clock generated by the clock generator 27. Specific examples in the data transmission system are Peripheral Components Interconnect bus (PCI bus), Card bus, and the like.
However, there are problems as mentioned below, in the data processing terminal system in the second conventional example.
In the data processing terminal system in the second conventional example, the error correction process, the encoding/decoding process, the identification data adding/removing process, and the like are carried out in the identification data processing circuit of the decoder (DEC) 71, the encoder (ENC) 72, and the microwave transmitting and receiving unit interface 73 in the microwave transmitting and receiving unit 17. For this reason, in the data processing terminal system in the second conventional example, the data processing terminal system becomes larger in size due to a built-in circuit for carrying out such processes in the microwave transmitting and receiving unit 17.
In the data processing terminal system in the second conventional example, the reception data buffer circuit, the transmission data buffer circuit, and the timing adjusting circuit are required, which are related to the timing adjusting process. Therefore, in the data processing terminal system in the second conventional example, the data processing terminal system becomes larger in size due to the circuit incorporated into the microwave transmitting and receiving unit 17 and the microprocessor signal processing unit 18 (the microwave transmitting and receiving unit interface 73 and the microprocessor signal processing unit interface 74) to carry out the timing adjusting process.
The data processing terminal system that can realize downsizing is desired.
In the data processing terminal system in the second conventional example, the microwave transmitting and receiving unit 17 incorporates the identification data processing circuit of the decoder (DEC) 71, the encoder (ENC) 72, and the microwave transmitting and receiving unit interface 73. For this reason, in the data processing terminal system in the second conventional example, extra power is consumed by a circuit for carrying out such processes. In general, the power consumption is proportional to the signal processing clock frequency (the reception symbol clock and the transmission symbol clock). Therefore, the power consumption is increased if an operation frequency of the microprocessor signal processing circuit (CPU) 75 becomes higher with the increase in a signal capacity.
In the data processing terminal system in the second conventional example, the microwave transmitting and receiving unit 17 and the microprocessor signal processing unit 18 (the microwave transmitting and receiving unit interface 73 and the microprocessor signal processing unit interface 74) incorporate the reception data buffer circuit, the transmission data buffer circuit, and the timing adjusting circuit, in order to carry out the timing adjusting process. For this reason, in the data processing terminal system in the second conventional example, the extra power is consumed by a circuit for carrying out the timing adjusting process.
The data processing terminal system that can realize low power consumption is desired.
In the data processing terminal system in the second conventional example, the microwave transmitting and receiving unit 17 incorporates the identification data processing circuit of the decoder (DEC) 71, the encoder (ENC) 72, and the microwave transmitting and receiving unit interface 73. For this reason, in the data processing terminal system in the second conventional example, a heat generated in accordance with the transmission and reception (the input and output) of the signal is excessively increased due to the circuit for carrying out such processes. The heat is increased in addition to the power consumption if the operation frequency of the microprocessor signal processing circuit (CPU) 75 becomes higher with the increase in the signal capacity. If the signal processing clock frequency is made higher due to the increase in the transmission capacity, the power consumption by the decoder (DEC) 71, the encoder (ENC) 72, and the microwave transmitting and receiving unit interface 73 increases, leading to a cause of the increase in the heat.
In the data processing terminal system in the second conventional example, the microwave transmitting and receiving unit 17 and the microprocessor signal processing unit 18 (the microwave transmitting and receiving unit interface 73 and the microprocessor signal processing unit interface 74) incorporate the reception data buffer circuit, the transmission data buffer circuit, and the timing adjusting circuit, for the purpose of carrying out the timing adjusting process. For this reason, in the data processing terminal system in the second conventional example, the heat generated in accordance with the transmission and reception (the input and output) is excessively increased due to the circuit for carrying out the timing adjusting process.
The data processing terminal system that can realize low heat generation is desired.
If the microwave transmitting and receiving unit 17 has a shape similar to a card, the condition for radiating heat generated by the microwave transmitting and receiving unit 17 is set more strictly than usual. Therefore, manufacturing cost increases for realizing a configuration in which the heat generated by the microwave transmitting and receiving unit 17 can be fully radiated.
In the data processing terminal system in the second conventional example, the microwave transmitting and receiving unit 17 and the microprocessor signal processing unit 18 (the microwave transmitting and receiving unit interface 73 and the microprocessor signal processing unit interface 74) incorporate the reception data buffer circuit, the transmission data buffer circuit, and the timing adjusting circuit, for the purpose of carrying out the timing adjusting process. For this reason, in the data processing terminal system in the second conventional example, the manufacturing cost increases excessively for manufacturing the circuit that carries out the timing adjusting process.
The data processing terminal system that can realize the reduction in cost is desired.
In the data processing terminal system in the second conventional example, there is a possibility that the timing adjusting process causes a transmission delay and the reduction in throughput. This problem becomes more apparent as the signal capacity increases in a portion between the microwave transmitting and receiving unit 17 (the microwave transmitting and receiving unit interface 73) and the microprocessor signal processing unit 18 (the microprocessor signal processing unit interface 74).
The data processing terminal system that can prevent the reduction in the throughput is desired.
In conjunction with the above, a software radio apparatus is disclosed in Japanese Laid Open Patent Application (JP-P2001-44882A). The software radio apparatus is configured to have one or more antennas, an antenna control unit, a radio signal processing unit, a signal processing unit, and an external interface unit. Processors are respectively incorporated into the antenna control unit, the radio signal processing unit, and the external interface unit. Additionally, a signal interface for communicating the control data is provided between the above respective units and the signal processing unit. The software radio apparatus is characterized by having a configuration, in which each unit described above controls its own operation in software by using the incorporated processor, based upon the control data on the signal interface. Here, the antenna carries out the transmission and reception of the radio signal. The antenna control unit carries out switching of the transmission and reception of the antenna, directivity control of the antenna, and the like. The radio signal processing unit, at the time of the reception, receives the signal from the above-mentioned antenna control unit, and carries out such signal processing as frequency conversion into the IF frequency or the baseband, band limiting, and level adjustment A/D conversion. The radio signal processing unit, at the time of the transmission, after the signal processing like D/A conversion band limiting for the supplied signal, carries out frequency conversion for the supplied signal into the RF frequency, and outputs the signal to the antenna control unit. The signal processing unit, at the time of the reception, receives the reception signal digitized by the radio signal processing unit, and carries out demodulation signal processing. The signal processing unit, at the time of the transmission, has a function of carrying out modulation signal processing to a signal supplied through an external interface unit, and outputting the processed signal to the radio signal processing unit. The signal processing unit also has a configuration in which it is possible to carry out the control of the foregoing by the incorporated processor, and to switch at least a part of the software necessary for the operation of the processor. The external interface unit, at the time of the reception, outputs the signal to which the demodulation signal processing is carried out by the signal processing unit, achieving matching with the external interface. The external interface unit, at the time of the transmission, outputs to the signal processing unit, achieving interface matching with an external apparatus.
Also, a data transmission system is disclosed in Japanese Laid Open Patent Application (JP-P2000-92142A). The data transmission system is characterized by having a transmitting unit for transmitting a signal obtained by adding predetermined frequency conversion data modulated with sub data outside the band of modulation output of main data to be transmitted; and a receiving unit for extracting the above-mentioned frequency conversion data from reception output of the transmission signal, controlling a signal as a reference for the frequency conversion on the reception side based upon the extracted frequency conversion data, and decoding the above-mentioned sub data.
Also, a signal transmitting apparatus is disclosed in Japanese Laid Open Patent Application (JP-P2000-151553A). The signal transmitting apparatus, on the transmission side, carries out the frequency conversion to an IF signal and transmits the converted IF signal. The signal transmitting apparatus, on the reception side, carries out the frequency conversion to a received signal to obtain an IF signal. A section of generating a pilot signal and a section of adding the pilot signal to the IF signal are provided on the side of the transmission. A section of extracting the above-mentioned pilot signal and a section of carrying out the frequency conversion to the above-mentioned pilot signal are provided on the side of the reception. The signal transmitting apparatus is characterized by carrying out the frequency conversion by using the above-mentioned pilot signal obtained by the frequency conversion as a local signal, to obtain the IF signal.
Also, a radio base station apparatus and a resource data checking method are disclosed in Japanese Laid Open Patent Application (JP-P2002-64845A). The radio base station apparatus is characterized by having a communication processing section in which the configuration of a hardware resources is optionally changeable in accordance with set resource data; and a base station controlling section for checking the resource data of the hardware resources set to the communication processing section with prerecorded resource management data in a constant time interval, and for changing the configuration of the communication section in accordance with a checking result.